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一、PCIe protocol and reference clock requirements
1. What is PCIe?
PCI Express (Peripheral Component Interconnect Express) is a high-performance, high-bandwidth serial bus standard used to connect various hardware devices inside a computer, such as graphics cards, storage devices (SSDs), network cards, etc. It replaces the traditional PCI and AGP buses, and has become the core interconnect technology of modern computer systems with its high speed, low latency and strong scalability.
PCIe supports multiple rate versions, including PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0 and PCIe 6.0, each of which doubles the bandwidth of the previous generation.
PCIe 6.0 was released in 2022, with a single-channel rate increased to 64 GT/s, and the introduction of PAM4 modulation technology, doubling the bandwidth again. At the same time, PCIe 6.0 also adds FEC (forward error correction) function to deal with signal attenuation problems in high-speed transmission.
Figure 1: PCIE 6.0 protocol standard
2. The key role of PCIe reference clock
In the PCIe system, the reference clock is the core component to ensure the accuracy and stability of data transmission. Its main functions include:
· Synchronous data transmission: Provide accurate clock signals for SerDes (serializer/deserializer) to ensure synchronization between the transmitter and the receiver.
· Reduced bit error rate: High-precision clock reduces signal jitter and reduces data transmission bit error rate (BER).
· Support multi-device collaboration: In complex architectures such as CXL and NVMe-oF, the reference clock needs to achieve phase alignment between multiple devices.
The reference clock under the PCIE protocol is basically 100MHz HCSL output, which is required to ensure the correctness and stability of data transmission and solve clock jitter, offset and noise problems.
With the upgrade of PCIe version, the performance requirements of reference clock have also been greatly improved. The following table shows the requirements of different PCIe protocol versions for reference clock RMS jitter:
Table 1: Requirements of different PCIe protocol versions for reference clock RMS jitter
二、YXC HCSL output differential crystal oscillator: an ideal choice to meet PCIe 5.0 clock requirements
In order to meet the stringent requirements of PCIe 5.0 for reference clock, it is recommended to use YXC differential oscillator YSO230LR series and YSO231LJ series of Yangxing Technology. These two products have become the ideal choice for PCIe 5.0 reference clock with their excellent performance and reliability.
YXC product advantages:
· Ultra-low jitter: Phase jitter can reach 0.05ps (typ.) RMS, meeting the stringent requirements of PCIe 5.0 and ensuring signal integrity;
· High stability: The optimal total frequency difference can reach ±25ppm @ -40~﹢85℃;
· Differential output: Supports multiple differential outputs such as HSCL, LVDS, and LVPECL;
· Miniaturization: Provides a 2.5*2.0mm compact design to adapt to high-density motherboard layout;
· Wide temperature range: Provides wide operating temperature options such as -40℃~﹢105℃ and -40℃~﹢125℃.
